This invention relates to a test apparatus for testing whether a semi-conductor memory device under test can perform correct read and write operations so that the apparatus can analyze the cause of any faults that are detected.
The general operational procedure of the semiconductor memory testing apparatus is first to generate an address and write-in data by the pattern generator, to access the memory under test using the generated address and to write in said write-in data, to access and read out the memory under test using said address, and to compare the read-out data with an expected data or with a correct data to inspect whether the memory device carries out the correct read/write operation. There have been proposed a number of patterns appropriate for such evaluation as the sequence of address generation, that is, the control of the address pattern for writing and reading. The so-called "Walking pattern", "Galloping pattern" and "Ping-Pong pattern" are well known patterns. The testing apparatus of this kind is in general designed to be able not only to test whether a memory device is defective or not but to detect faulty spots if the device is defective and further to analyze the cause of a fault.
In the prior art memory testing apparatus, when an inconsistency between a read-out data and an expected data occurs even only once during the test, the test is halted and the faulty memory is simply rejected as an unacceptable product. As the integration density of memory devices is getting high and thus the capacity thereof increases, the frequency of occurrence of faulty products grows while the available percentage decreases if the product is rejected due to only one faulty spot and, as a consequence, the cost of the acceptable products will be raised. Accordingly, it has been proposed to provide error correcting means when the faulty spots in a memory device are few, so that some percentage of faulty products all of which would conventionally be rejected can be saved as acceptable products. Another proposed possibility of saving some percentage of the faulty products is to use only the normally operating area of the memory device, leaving some area containing faulty spots unused. In this case, it is necessary to decide, for example, that when the number of faulty spots is less than a predetermined value, the memory device is acceptable, and when the number is more than the predetermined value, the device is unacceptable. In testing of this kind, it is usual to access one address twice or more for reading out during testing. Accordingly, it may not be allowed to judge the memory device acceptable only from the result that such a simple counting is less than a predetermined value. For this reason, such judgement that the product is acceptable if the number of faulty spots thereof is less than a predetermined value has not been employed.
Generally, the analysis of the causes of faulty spots of a memory device is performed such that when disagreement between the data read out and an expected data is detected, the address where the disagreement was detected is used as an address to access a fault-address memory and, to store therein the disagreement data and after completing the entire test, the contents of the fault-address memory are read out and supplied to the CPU to perform the fault analysis according to a predetermined procedure. In order to take the contents of the fault-address memory into the CPU, conventionally the CPU sequentially accesses each address of the fault-address memory and the read out data are taken into the CPU. The CPU judges whether the read out data are faulty or not and in which address the fault occurred. Alternatively, all the contents of fault-address memory are temporarily transferred to the storage of the CPU and then the CPU examines the contents of all of the addresses corresponding to the transferred data to perform the fault analysis.
However, in order to access each address of the fault-address memory and to take the content thereof into the CPU, it is necessary to have time equal to the product of one input/output cycle time multiplied by the number of addresses in the fault-address memory; therefore, if the number of addresses to be accessed is considerably large it takes a fairly long time for the CPU to read out the contents of the fault-address memory. In particular, if there are many faulty spots the CPU needs to fetch and store the corresponding faulty addresses, which does not cause a problem. However, in case of a large number of addresses with a few faulty spots, there is the disadvantage of taking a considerable time for detecting the few faulty spots.